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SX1231 Radio

SX1231 radio transceiver is a completely different beast than the SX1212. Compared to the SX1212, the SX1231 has superior RF performance:

  • Supports both 55,555bps and 200Kbps over-the-air bitrates.
  • Transmitter:
    • Much cleaner signal: PLL frequency synthesizer has much lower phase noise and spurs, while achieving lock time of 80 microseconds typical.
    • Modulation shaping. Complies with 216KHz channel bandwidth requirement of Mode-2.
    • +13dBm standard power output, +17dBm optional with external RF switch.
  • Receiver:
    • much wider dynamic range (range of signal amplitude into receiver).
    • RSSI dynamic range of 115dB.
    • superior handling of strong adjacent signals, also known as blocking immunity.
  • lower external component count: PLL is implemented entirely on silicon, no external tank circuits or loop filters.
  • 100nA leakage current in sleep mode, with worst case wake-up time of half millisecond.
  • frequency range coverage: 290 to 1020MHz.
  • packet engine optional feature of AES 128bit fixed key cipher. (not used with Dash7)

Design Notes

SX1231 transmitter portion is simple and provides good performance. However, the SX1231 receiver uses a digital demodulator, which in this implementation requires extra care with regards to AGC. This device has both AGC from LNA gain setting on RF front-end, and “digital” AGC on the ADC output after mixer (at baseband). Additionally, in the tradition of fine Swiss engineering, the LNA portion of AGC is performed only upon receiver start-up.

  • Fortunately, DASH7 bandwidth is wide enough to not require any correction of crystal frequency error. Automatic frequency correction (AFC) should be avoided with this transceiver, unless you can tolerate higher CPU overhead. Because, again in the fine tradition of Swiss engineering, AFC is performed only on receiver start-up. Consider ourselves lucky that DASH7 is not narrow-band enough to require AFC. SX1232 addresses much of these issues.
  • In the SX1231 receiver, having the zero I.F. architecture (see Direct-conversion_receiver) is great for image rejection, however the artifact of that is requiring a DC cutoff filter. This cutoff filter must be adjusted carefully when low modulation-index FSK is used.
  • SX1231 is also available with Freescale MC9S08QE32 in single package.

SX1231 Mode 2 Implementation Notes

Packet mode of radio is used in unlimited length configuration. For FIFO access to send and receive radio packets: SPI port on SX1231 allows use of DMA with with CPU SPI port, greatly reducing the interrupt rate overhead of CPU. This is due to a “burst mode” method of FIFO access in the radio, which allows chip select to remain asserted throughout transfer.

SX1231 Mode 2 radio interrupt configuration

Signal name SX1231 pin description
PacketSent DIO0 termination of transmission
FifoLevel DIO1 flow control during transmit and receive
RxReady DIO4 RSSI measurement on receiver start-up

FifoLevel is used to initiate DMA transfer over SPI during transmission and reception. FifoLevel indicates the count of bytes in radio FIFO are above or below the FifoThreshold.

RxReady is used upon CCA (energy detection) due to SX1231 receiver behavior where if zero RF energy is detected when starting reception, RxReady signal will not assert. Absence of RxReady after receiver start indicates that no energy exists on radio channel. Otherwise if RxReady is asserted, then RSSI measurements are taken.

SX1231 Mode-2 Hi-Rate 200Kbps FSK-0.5 support

Due to the inherent characteristic of frequency modulation to increase occupied bandwidth when modulated frequency increases given a constant deviation, Hi-Rate FSK-0.5 will occupy slightly more bandwidth compared to 55555bps FSK-1.8 modulation. SX1231 receiver will use 83KHz single-side bandwidth for 55555bps mode, and 100KHz single-side bandwidth for 200Kbps mode. Best receiver results were obtained using a DC-cutoff setting of 0.25%.

Sync word detection for Dash7 Mode2

Sync word byte-ordering is selected for CC430 compatability: LSbyte first. For example in the case of 0x0b67 sync word: 0x67 is sent first in time, then 0x0b. MSbit is sent first.

SX1231 Mode 1 Implementation Notes

Mode-1 is implemented using STM32 timer and STM32 DMA with bit-synchronizer on radio disabled, see mode 1 generic description.

SX1231 Mode 1 Transmitter

The SX1231 makes a much better Mode-1 transmitter than the SX1212, due to its superior PLL cleanliness. (low jitter transmission)

SX1231 Mode-1 Receiver

  • Like the SX1212, the SX1231 contains a similar bit-synchronizer in the receiver. This bit synchronizer is useless for Mode-1 due to Mode 1's behavior of constant varying frequency (varying bitrate). This bit synchronizer would only be useful if it kept constant frequency while only allowing phase shift in order to correctly sample demodulated data.
  • Mode 1 reception is implemented on SX1231 with bit synchronizer OFF in continuous mode. This provides direct access to demodulator on DATA pin. However, the default configuration of digital AGC (DAGC) results in a far too glitchy data output from receiver. To resolve this, DAGC is configured with fixed low gain, resulting in glitch-free received data. This results in superior Mode-1 reception compared to SX1212, due to the cleaner PLL on SX1231.
  • Dynamic range (signal strength range) of Mode-1 receiver is limited when LNA gain is fixed. At maximum fixed LNA gain, best sensitivity is obtained, yet overload can occur at signal strengths as low as -20dBm. If wider dynamic range is required, radio driver firmware can be conditionally compiled to enable LNA-gain AGC in firmware. When LNA-gain AGC is continuously performed, then signal strength can rise (without distortion) to the damage level of radio chip, while still maintaining maximum sensitivity to weak signal.
opentag/radios/sx1231.txt · Last modified: 2012/03/07 01:16 by jpnorair