SX1231 radio transceiver is a completely different beast than the SX1212. Compared to the SX1212, the SX1231 has superior RF performance:
SX1231 transmitter portion is simple and provides good performance. However, the SX1231 receiver uses a digital demodulator, which in this implementation requires extra care with regards to AGC. This device has both AGC from LNA gain setting on RF front-end, and “digital” AGC on the ADC output after mixer (at baseband). Additionally, in the tradition of fine Swiss engineering, the LNA portion of AGC is performed only upon receiver start-up.
Packet mode of radio is used in unlimited length configuration. For FIFO access to send and receive radio packets: SPI port on SX1231 allows use of DMA with with CPU SPI port, greatly reducing the interrupt rate overhead of CPU. This is due to a “burst mode” method of FIFO access in the radio, which allows chip select to remain asserted throughout transfer.
|Signal name||SX1231 pin||description|
|PacketSent||DIO0||termination of transmission|
|FifoLevel||DIO1||flow control during transmit and receive|
|RxReady||DIO4||RSSI measurement on receiver start-up|
FifoLevel is used to initiate DMA transfer over SPI during transmission and reception.
FifoLevel indicates the count of bytes in radio FIFO are above or below the
RxReady is used upon CCA (energy detection) due to SX1231 receiver behavior where if zero RF energy is detected when starting reception,
RxReady signal will not assert. Absence of
RxReady after receiver start indicates that no energy exists on radio channel. Otherwise if
RxReady is asserted, then RSSI measurements are taken.
Due to the inherent characteristic of frequency modulation to increase occupied bandwidth when modulated frequency increases given a constant deviation, Hi-Rate FSK-0.5 will occupy slightly more bandwidth compared to 55555bps FSK-1.8 modulation. SX1231 receiver will use 83KHz single-side bandwidth for 55555bps mode, and 100KHz single-side bandwidth for 200Kbps mode. Best receiver results were obtained using a DC-cutoff setting of 0.25%.
Sync word byte-ordering is selected for CC430 compatability: LSbyte first. For example in the case of
0x0b67 sync word:
0x67 is sent first in time, then
0x0b. MSbit is sent first.
Mode-1 is implemented using STM32 timer and STM32 DMA with bit-synchronizer on radio disabled, see mode 1 generic description.
The SX1231 makes a much better Mode-1 transmitter than the SX1212, due to its superior PLL cleanliness. (low jitter transmission)
DATApin. However, the default configuration of digital AGC (DAGC) results in a far too glitchy data output from receiver. To resolve this, DAGC is configured with fixed low gain, resulting in glitch-free received data. This results in superior Mode-1 reception compared to SX1212, due to the cleaner PLL on SX1231.